* work with architecture and software teams to ensure micro-architecture and design is fully verified/validated across multiple platforms

* contribute significantly to verification infrastructure development

* development of system verilog/uvm based protocol/traffic generators/checkers, development of test plan based on functional requirements

岗位要求：

masters degree desired, bachelor's degree in cs/ee is required. 5+ years of relevant experience in asic verification field.

* should have worked on developing/implementing test plans at the chip-level for complex asics.

* fluent in system verilog and scripting languages such as python or perl.

* must have intimate knowledge of uvm methodology.

* experience in the verification of soc and other ips such as cpu subsystem, ethernet, pcie, ddr, serdes etc.

* knowledgeable about assertions and functional coverage

* experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.

* very good communication skills and ability and desire to work in a geographically diverse team environment.

* will be responsible for definition, development and execution of self-checking tests for complex digital asics

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